FIGS. 1A and 1B respectively show typical examples based on conventional mounting schemes. Referring to FIG. 1A, a semiconductor chip 12 is die-bonded on a die stage 11 of a lead frame, and then bonding pads formed on a chip face of the semiconductor chip 12 and outer leads 14 of the lead frame are wire-bonded together by bonding wirings 13. The bonding is carried out by a thermocompression bonding procedure during which ends of the bonding wires which have been heated are placed on members which are to be bonded. According to the above wire bonding procedure, it becomes possible to automatically connect the semiconductor chip 12 and the lead frame 14. During the wire bonding procedure, the bonding pads are processed in series.
FIG. 1B shows a TAB-based mounting structure. A plurality of parts which are to be bonded are prepared on the chip face of the semiconductor chip 12. Tape leads 17, each having a plurality of corresponding leads, are arranged on the parts on the chip face. By using bumps 16, a thermocompression bonding procedure is carried out so that the tape leads 17 are bonded to the parts via the bumps 16 at one time. After the bonding procedure on the semiconductor chip 12 and the tape leads 17 is carried out, a positioning procedure on the tape leads 17 and the outer leads 14 is carried out. Hence, the tape leads 17 and the outer leads 14 are bonded together in such a manner that plating layers of the tape leads 17 and the outer leads 14 form eutectic crystals. It is possible to provide the bumps 16 on the bonding pads of the semiconductor chip 12 or provide the bumps 16 on the end portions of the tape leads 17.
By using the TAB procedure, it becomes possible to execute a bonding procedure on a plurality of bonding parts at one time. As compared with the bonding wires 13, it is easy to fine produce the tape leads 17. For these reasons, the TAB procedure can satisfy recent requirements of increase in the number of pins and increase in the integration density.
A resin molded semiconductor device can be produced by sealing a bonded assembly with a molded resin.
The feature scale of pattern is being reduced. However, there are limits upon the number of pins and the integration density while the shapes of packages being used at present are maintained. The conventional package structures have limits upon an increase in the integration density arising from a package size, that is, an internal space of the package.
The conventional mounting techniques for increasing the number of pins and the integration density by reducing wiring patterns and the pitch of electrodes are indented to improvement in the density in the two-dimensional area.
Recently, semiconductor devices having a plurality of semiconductor chips provided inside a package have been proposed. For example, Japanese Laid-Open Patent Publication No. 56-17050 shows a semiconductor device in which semiconductor chips are mounted on both sides of a supporting base and the semiconductor chips are connected to the lead frames by bonding wires. After bonding, the semiconductor chips are sealed by a mold resin.
Japanese Laid-Open Patent Publication No. 56-137665 discloses a semiconductor device in which at least two pellets are disposed on both sides of lead frames and electrode parts of the pellets are bonded to the lead frames (by soldering bumps). After bonding, the pellets are sealed by molding.
Further, "NIKKEI MICRODEVICES", Nov., 1989, discloses a structure in which four LSI chips, each being sealed by molding, are successively stacked in order to improve the integration density per area.
However, the semiconductor device disclosed in Japanese Laid-Open Patent Publication No. 56-17050 has the following disadvantages. First, it is impossible to considerably reduce the distance (pitch) between adjacent pins because the wire bonding is used. Second, it is necessary to bend the bonding wires (see FIG. 1A), and it is difficult to produce a thin structure because of use of the supporting base.
The semiconductor device disclosed in Japanese Laid-Open Patent Publication No. 56-137665 has the following disadvantages. In light of production process, it is difficult to directly adhere the semiconductor chip on the lead frames by means of soldering bumps. Particularly, it is very difficult to precisely attach a semiconductor chip to the lead frames to which another semiconductor chip has been attached. If an positional error occurs, the semiconductor chips may be exposed from the molded resin.
The structure disclosed in "NIKKEI MICRODEVICES" has a first disadvantage in that a thin structure cannot be produced because the four molded LSI chips are successively stacked and a second disadvantage in that a complex step is needed to adhere the four LSI chips.